The present invention relates to a semiconductor random access memory (RAM) device and, in particular, to an improvement in application of a write data signal to memory cells which enables to small-size the RAM device of, particularly, a multiport type.
In the semiconductor RAM device, there are a single port type having a single port through which the RAM is accessed by a single processor and a multiport type having a plurality of ports through which the RAM can commonly be accessed by a plurality of processors.
Generally speaking, a semiconductor RAM device has a memory cell array comprising a plurality of memory cells arranged in rows and columns of a matrix. Each of the memory cells comprises a data holding element which is, usually a flipflop circuit having a pair of terminals. In order to write a data signal to the data holding element, a high level or "1" signal and a low level or "0" signal are simultaneously applied to the pair of terminals. It is provided that when "1" signal is applied to first one of the pair of terminals while "0" signal being applied to the other or second one of the pair of terminals, the data holding element holds the data signals of "1" and "0" at the first and the second terminals, respectively. On the other hand, when "0" signal is applied to the first terminal while "1" signal being applied to the second terminal, the data holding element holds the data signal of "0" and "1" at the first and the second terminals, respectively. The memory cell array further comprises a plurality of word lines extending along the rows and a plurality of digit or bit lines extending along the columns.
In a typical RAM of the single port type, a single word line is commonly connected to memory cells in each of the rows. One pair of the digit lines are commonly connected to the memory cells in each of the columns. In each of the memory cells, the two digit lines of one pair are connected to the first terminal and the second terminal of the data holding element through a first and a second gate, respectively. The first and the second gates are commonly connected to the single word line. When the single word line is activated, the first and second gates are opened and the two digit lines are electrically connected to the first and second terminals through the first and the second gates opened, respectively. Thus, the "0" and "1" signals are read out from the data holding element in the memory cell onto the two digit lines, respectively. Alternatively, when the "0" and "1" signals are applied to the digit lines, respectively, "0" and "1" signals are held at the two terminals of the data holding element, respectively. Thus, the pair of two digit lines for one column is used for transmission of both of the write data signal and the read data signal, that is, used as a write signal line pair and also as a read signal line pair.
In another known single port type RAM, an additional word line is provided for each of the rows and additional column line is provided for each of the columns. In this type of RAM, the additional word line and the additional column line are only used for reading the data signal. Therefore, the additional word line and the additional column line are referred to as a reading word line and a read signal line, respectively. The existing pair of digit lines and the corresponding word line are used only for writing data signals. The pair of digit lines are, therefore, referred to as a write signal line pair and the corresponding word line is referred to as a writing word line.
In any one of the single port type RAM devices, each one of memory cells is formed to have the first and the second terminals of the data holding element which are disposed at opposite sides of the data holding element in the row direction. Accordingly, the first and the second gates are disposed at the opposite sides of the data holding element outwardly from the first and the second terminals. Therefore, the two digit lines of one pair are disposed outward of the first and the second gates. This means that the size of the memory cell is relatively large in the row direction. Further, the digit lines of one memory cell are disposed adjacent digit lines of other memory cells adjacent in the row direction. Accordingly, there is a problem of cross talk between the adjacent digit lines.
In order to avoid the cross talk, a space between adjacent columns must be sufficiently enlarged. This results in large size of the memory cell array. Alternatively, a ground line is disposed in the space between adjacent columns so that the space can be reduced. However, reduction of the size of the memory cell array is limited by provision of the ground lines between adjacent memory cells.
In the semiconductor RAM of the multiport type, a number of the writing word lines and a number of the reading word lines for each row of the memory cell array are determined by requirement of processors connected to the plurality of ports. Numbers of the corresponding write signal line pairs and read signal lines for each column of the array are determined in dependence of the numbers of the writing and reading word lines for each row.
When only one of processors requires for writing data into the RAM and the other processors require only to read the data from the RAM, one writing word line and one write signal line pair are provided for one row and one column of the array, respectively. This has a problem similar to the single port RAM as described above.
When a plurality of processors, for example, two processors require for writing data into the RAM, two writing word lines and two write signal line pairs are provided for one row and for one column of the matrix array, respectively. In this case, since the digit lines of one pair are disposed adjacent to digit lines of another pair in one of memory cells, there is a further cross talk problem between adjacent digit lines of different pairs for different ports. In order to resolve the problem, ground lines are also provided between adjacent digit lines of different write signal line pairs. This results in increase of size of each memory cell and therefore of RAM device itself.